4.3 Two-Supply Emitter Bias

James M. Fiore; NSCC

4.3 Two-Supply Emitter Bias

For proper functioning, the collector-base junction needs to be reverse-biased and the base-emitter junction needs to be forward- biased. For an NPN transistor that means that the collector must be at the highest potential, the base somewhat lower and the emitter at the lowest potential of the three. One way of doing this is to apply the usual positive supply to the collector, but instead of using a second potential at the base, the base is tied to ground through a resistor. The requisite forward-bias on the base-emitter is then achieved by connecting the emitter to a negative power supply. This circuit configuration is shown in Figure 4.3.1 using an NPN device. We shall refer to this as two-supply emitter bias.

Figure 4.3.1: Two-supply emitter bias, NPN version.

We can derive an equation for the collector current by applying KVL to the baseemitter loop:

$V_{EE} = V_{R_B}+V_{BE}+V_{R_E}$

$V_{EE} = I_B R_B+V_{BE}+I_E R_E$

Recalling that I_B = I_C /β and I_E ≈ I_C ,

$V_{EE} = (I_C/ \beta )R_B+V_BE+ I_C R_E$

Solving for I_C we arrive at

$I_C = \frac{|V_{EE}|−V_{BE}}{R_E+R_B / \beta}$

(4.3.1)

The absolute value has been added to the emitter supply voltage so there is no confusion regarding the sign of this potential in the equation.

The thing to notice about Equation 4.3.1 is that β R_E ≫ R_B/β , then the equation reduces to only partly determines the collector current. In fact, if we can make R_E≫R_B/βR_E≫R_B/β, then the equation reduces to

$I_C \approx \frac{|V_{EE}|-V_{BE}}{R_E}$

(4.3.2)

It is relatively easy to achieve the R_E ≫ R_B/β stipulation. Given typical values of β, this will be the case if R_E is approximately equal to or larger than R_B. What we find in this instance is that almost all of the emitter supply drops across R_E to establish a stable I_C with β playing virtually no role. If β changes, the result will be an inverse change in I_B with I_C remaining largely unchanged.

Now that we have the collector current, any other current or voltage in the circuit may be derived by applying Ohm’s law, KVL and the like. For example, to find V_C , the voltage from the collector to ground,

$V_C = V_{CC}-V_{R_C}$

$V_C = V_{CC}-I_C R_C$

And to find the transistor’s collector-emitter voltage, V_CE ,

$V_{CE} = V_{CC}+|V_{EE}|-V_{RC} -V_{RE}$

$V_{CE} = V_{CC}+|V_{EE}|-I_C R_C -I_C R_E$

$V_{CE} = V_{CC}+|V_{EE}|-I_C (R_C+R_E )$

Note that V_CE can also be found via V_CE = V_C − V_E . Dropping voltages along the base-emitter loop yields

$V_E = -V_{R_B} -V_{BE}$

$V_E = −I_B R_B -V_{BE}$

(4.3.4)

Also, it is to our advantage to develop the DC load line for this configuration. The load line can serve as a “sanity check” for our computations. To find the endpoints, I_C(sat) is the maximum current and will occur when V_CE = 0 . If we imagine the current rising as VCE collapses, eventually all of the available supply voltage will have dropped across RC and R_E. Thus

$I_{C(sat)} = \frac{V_{CC}+|V_{EE}|}{R_C+R_E}$

(4.3.4)

Similarly, VCE(cutoff) occurs when I_C = 0. That means that there will be no potentials across R_Cand R_E. Therefore, V_CE “absorbs” the entire available source voltage.

$V_{CE (cutoff )} = V_{CC}+|V_{EE}|$

(4.3.5)

Do not attempt to memorize all of the myriad equations presented. There are simply too many variations on the theme and it will only get worse when other biasing configurations are introduced. Instead, remember how to find the collector current and then get in the habit of applying Ohm’s law and KVL to derive whatever else you may need.

At this point a comprehensive example is called for.

Example 4.3.1

Assuming β = 100, plot the Q point (I_C and V_CE ) on the load line for the circuit of Figure 4.3.2.

Using Equation 4.3.1:

$I_C = \frac{|V_{EE} |-V_{BE}}{R_E+R_B / \beta}$

$I_C = \frac{10-0.7}{2.7k \Omega +4.1 k \Omega /100}$

$I_C = 3.38 mA$

Noting the relative sizes of R_E and R_B, the approximation should be close.

$I_C = \frac{|V_{EE} |-V_{BE}}{R_E}$

$I_C = \frac{10-0.7}{2.7 k \Omega}$

$I_C = 3.44 mA$

To find VCE we can use the equation derived above (Equation 4.3.3).

$V_{CE} = V_{CC} +|V_{EE}|-I_C(R_C+R_E )$

$V_{CE} = 20 V+10 V-3.38mA(3.3 k \Omega +2.7k \Omega )$

$V_{CE} = 9.72 V$

Now calculate the load line endpoints:

$I_{C(sat)} = \frac{V_{CC}+|V_{EE} |}{R_C+R_E}$

$I_{C(sat)} = \frac{20 V+10V}{3.3K \Omega +2.7K \Omega}$

$I_{C(sat)} = 5 mA$

$V_{CE (cutoff )} = V_{CC} +|V_{EE}|$

$V_{CE (cutoff )} = 20 V+-10 V$

$V_{CE (cutoff )} = 30 V$

The load line for the circuit in Example 4.3.1 is shown in Figure 4.3.3.

Figure 4.3.3: DC load line for the circuit of Figure 4.3.2.

Note the proportions between voltage and current for the Q point. The voltage is a little less than one-third of the maximum while the current is a little more than two-thirds of its maximum.

Verification of Stability

The claim was made that two-supply emitter bias circuits like the one Figure 4.3.1 potentially have a stable Q point. If we were to plot a second Q point for a large change in β, it should hardly move, thus indicating very high stability. For example, doubling β to 200 results in I_C = 3.41 mA and V_CE = 9.53 V. The new Q point has edged just slightly closer to saturation, producing about a 1% change in current for a 100% change in β. Clearly, this configuration can produce very small changes in the Q point in spite of very large changes in β.

Computer Simulation

The two-supply emitter bias circuit of Figure 4.3.4 is simulated using the DC Bias function. A quick estimation shows that we expect about 2 mA of collector current (9.3 V/4.7 kΩ) and a collector voltage of about 8 volts (15 V − 2 mA 3.6 kΩ). We also expect a small negative potential at the base −I_BR_B ). Given typical β values for the 2N3904 (200-ish at this current, refer back to the data sheet), we expect a base current of around 10 to 15 μA, leaving us with a V_B of approximately −0.1 volts. The emitter voltage would be about 0.7 volts less than that, perhaps −0.8 volts or so.

In short, for a properly designed circuit of this type we expect V_B to be pretty close to 0 V and V_E to be about −0.7 volts.

Figure 4.3.4: Schematic for two-supply emitter bias simulation.

The results are shown in Figure 4.3.5. The node voltages agree with our estimations. Node 3 is the collector voltage, very close to the estimation. The results for the base voltage (node 2) and the emitter voltage (node 1) are also in line with the estimates.

Figure 4.3.5: Simulation results for twosupply emitter bias circuit

PNP Two-Supply Emitter Bias

While it is possible to create a PNP version of bias circuits by simply swapping out the device and then changing the signs of the power supplies, it is common to “flip” the entire circuit from top to bottom so that the emitter winds up on top and the collector on the bottom. One advantage of this is that, in a multi-transistor circuit schematic, all of the DC bias currents “run down the page”, that is, the collector currents flow from the top of the page to the bottom of the page. Figure 4.3.6 shows a PNP two-supply emitter bias circuit.

All of the device current equations and component voltage equations derived for the NPN version will hold for the PNP version. The differences to remember are that the voltage polarities will be reversed (what was positive in the NPN is negative in the PNP) and the current directions will be reversed (e.g., conventional current flows into the NPN’s collector but out of the PNP’s collector. For example, in the NPN we expect the base current to flow into the base terminal. This creates a small negative voltage at the base and a somewhat more negative voltage (by 0.7 V) at the emitter. In the PNP, the base current flows out of the base. This creates a small positive voltage at the base and results in the emitter being slightly more positive (by 0.7 V). This is perhaps best illustrated with an example.

Example 4.3.2

Assuming β = 100, determine the Q point and load line endpoints of the circuit of Figure 4.3.7.