4.4 Voltage Divider Bias

James M. Fiore; NSCC

4.4 Voltage Divider Bias

Another configuration that can provide high bias stability is voltage divider bias. Instead of using a negative supply off of the emitter resistor, like two-supply emitter bias, this configuration returns the emitter resistor to ground and raises the base voltage. So as to avoid issues with a second power supply, this base voltage is derived from the collector power supply via a voltage divider. The bias template is shown in Figure 4.4.1.

Let’s derive the equations for the load line. First, let’s consider the saturation and cutoff endpoints. For saturation, assume V_CE goes to 0. What resistances are left to limit the current?

$I_{C(sat)} = \frac{V_{CC}}{R_C+R_E}$

(4.4.1)

V_C_E(cutoff) occurs when I_C = 0 and that means that there will be no potentials across R_C and R_E. Therefore, V_CE takes on the entire available source voltage.

$V_{CE (cutoff )} = V_{CC}$

(4.4.2)

The key to finding the Q point (and pretty much any other current or voltage in the circuit) is to find I_C . To simplify the process, Thevenize the voltage divider as shown in Figure 4.4.2.

Figure 4.4.2a: Thevenizing the voltage divider.

Figure 4.4.2b: Thevenizing the voltage divider.

Figure 4.4.2c: Thevenizing the voltage divider.

By inspection of Figure 4.4.2b,

$V_{TH} = V_{CC} \frac{R_2}{R_1+R_2}$

$R_{TH} = R_1 || R_2 = \frac{R_1 R_2}{R_1+R_2}$

Now we can derive an equation for the collector current by applying KVL to the base-emitter loop of Figure 4.4.2c:

$V_{TH} = V_{R_{TH}} +V_{BE}+V_{R_E}$

$V_{TH} = I_B R_{TH} + V_{BE} + I_E R_E$

Recalling that I_B = I_C /β and I_E ≈ I_C ,

$V_{TH} = (I_C / \beta )R_{TH} + V_{BE}+I_C R_E$

Solving for I_C we arrive at

$I_C = \frac{V_{TH}-V_{BE}}{R_E+R_{TH} / \beta}$

(4.4.3)

Can we find a quick approximation for I_C as well? If we assume that the voltage divider of R₁ and R₂ is lightly loaded, in other words, that the divider current is much, much less than the base current, finding I_C is easy. The divider voltage yields the base voltage. We then subtract the 0.7 volt drop on the base-emitter and what’s left drops across R_E. From there it’s one short application of Ohm’s law to get I_E, which is approximately equal to I_C . But how do we know if the divider is lightly loaded in the first place without going through the Thevenin equivalent? Looking at Equation 4.4.3, as long as R_E ≫ R_T _H /β , we can ignore the second term in the denominator, leaving us with our quick approximation. Given typical values for β, as long as R₂ is not much larger than R_E, the approximation will be reasonably accurate.

Once I_C is obtained we can find the transistor’s collector-emitter voltage, V_CE ,

$V_{CE} = V_{CC}-V_{R_C}-V_{R_E}$

$V_{CE} = V_{CC}-I_C R_C-I_C R_E$

$V_{CE} = V_{CC}-I_C (R_C+R_E )$

(4.4.4)

Time for yet another thrilling illustrative example.

Example 4.4.1

Assuming β = 200, plot the Q point (IC and VCE ) on the load line for the circuit of Figure 4.4.3. Also determine the value of V_B.

Calculate the load line endpoints so we know the maximums.

$I_{C(sat)} = \frac{V_{CC}}{R_C+R_E}$

$I_{C(sat)} = \frac{15 V}{3.9K \Omega +3.3K \Omega}$

$I_{C(sat)} = 2.08mA$

$V_{CE (cutoff )} = V_{CC}$

$V_{CE (cutoff )} = 15 V$

To obtain the Q point, first find the Thevenin values.

$V_{TH} = V_{CC} \frac{R_2}{R_1+R_2}$

$V_{TH} = 15 V \frac{4.7k\Omega}{ 10 k\Omega +4.7 k\Omega}$

$V_{TH} = 4.8V$

$R_{TH} = R_1\|R_2 = \frac{R_1 R_2}{R_1+R_2}$

$R_{TH} = \frac{10 k \Omega \times 4.7 k\Omega}{10 k \Omega +4.7 k\Omega}$

$R_{TH} = 3.2k\Omega$

Using Equation 4.4.3:

$I_C = \frac{V_{TH} -V_{BE}}{R_E+R_{TH} / \beta}$

$I_C = \frac{4.8V-0.7V}{3.3 k\Omega +3.2 k\Omega /200}$

$I_C = 1.236mA$

Noting the relative sizes of R_E and R₂, the approximation should be fairly accurate.

$I_C = \frac{V_{TH}-V_{BE}}{R_E}$

$I_C = \frac{4.8V-0.7 V}{3.3k \Omega}$

$I_C = 1.242mA$

To find V_CE we can use Equation 4.4.4.

$V_{CE} = V_{CC}-I_C (R_C+R_E )$

$V_{CE} = 15V-1.236mA(3.9k \Omega +3.3 k \Omega )$

$V_{CE} = 6.1V$

As far as finding V_B is concerned, a decent approximation would be the value of V_TH because we have determined that the divider is lightly loaded. In a more general sense, we could also find the drop across R_E and then add V_BE. The approximation yields 4.8 volts and the more accurate method yields

$V_B = V_{BE} +I_C R_E$

$V_B = 0.7 V +1.236mA\times 3.3k \Omega$

$V_B = 4.78V$

The load line for the circuit in Example 5=4.4.1 is shown in Figure 4.4.4.

Figure 4.4.4 : DC load line for the circuit of Figure 4.4.3 .

Once again the proportions between voltage and current for the Q point appear to be proper when compared against the endpoints.

Verification of Stability

How much does the Q point move if β were to get cut half? Recalculating with a β of 100 yields I_C = 1.23 mA and V_CE = 6.14V. This represents a shift in both current and voltage of less than 1%. This will, of course, cause a near doubling of I_B but this will be hardly noticed here as the divider current is so much larger; approximately 15V/ (10 k + 4.7 k) or 1 mA versus about 1.23 mA/100 or 12.3 μA.

PNP Voltage Divider Bias

To create the PNP version of the voltage divider bias, we replace the NPN with a PNP and then change the sign of the power supply. As mentioned with the two-supply emitter bias, these circuits are usually flipped top to bottom resulting in the flow of DC current going down the page. All of the currents and component voltages are unchanged except that their directions and polarities are reversed. The current equations and so forth remain valid. Something a little odd-looking happens with the voltage divider bias, though: we end up with ground being the most positive potential and a negative supply at the bottom of the schematic. It works, but it’s an issue if we’re using a traditional positive supply elsewhere in the circuit. After all, why have two supplies where one will do? It turns out that we can make a positive supply version fairly easily. All we need to do is add the magnitude of the negative source voltage to the ground and power connections. This progression is shown in Figure 4.4.5.

There is nothing magic about this procedure. In essence, all we’ve really done is renamed the reference point. All of the individual component voltages remain unchanged. For example, looking at Figure 4.4.5c versus 4.4.5b, it is still the case that the top connection to R_E is more positive than the bottom connection to R_C by the voltage V_CC (although we did rename the supply to V_EE to be consistent with where it’s connected). What has happened is that all ground-referenced (i.e., single subscript) voltages have changed. For example, V_B in Figures 4.4.5a and 4.4.5b is the voltage across R₂ . In contrast, V_B in Figure 4.4.5c is the voltage across R₁ . That makes sense. If we move the reference then any voltage that is measured against the reference will change.

When analyzing the PNP voltage divider, we could simply parrot the collector current formula developed for the NPN, but there are other techniques. Two methods are illustrated in the following example.

Example 4.4.2

Assuming β=200, determine the Q point (I_C and V_CE) for the circuit of Figure 4.4.3. Also determine the values of V_C and V_B.

First off, R₂ (now on top) is around the same size as R_E so the approximation method should be accurate and we can assume the divider is lightly loaded.

Method One

We will focus on the base-emitter loop as usual because V_BE is a known potential. Our immediate goal is to find the voltage across R_E so that we can use Ohm’s law to find I_C. First we note that the voltage drop across R₂ is equal to the combined drops across R_E and V_BE. The drop across R₂ is found via the voltage divider rule.

$V_{R_2} = V_{EE} \frac{R_2}{R_1+R_2}$

$V_{R_2} = 15 V \frac{4.7k \Omega}{ 10 k \Omega +4.7k \Omega}$

$V_{R_2} = 4.8 V$

And

$V_{R_E} = V_{R_2}-V_{BE}$

$V_{R_E} = 4.8V-0.7V$

$V_{R_E} = 4.1V$

Therefore

$I_C = \frac{V_{R_E}}{R_E}$

$I_C = \frac{4.1 V}{3.3 k\Omega}$

$I_C = 1.24 mA$

Method Two

Here we will determine all voltages with respect to ground.

$V_B = V_{EE} \frac{R_1}{R_1+R_2}$

$V_B = 15 V \frac{10 k\Omega}{10 k \Omega +4.7 k\Omega}$

$V_B = 10.2 V$

The voltage from base to emitter has a − to + polarity, meaning it is a rise of 0.7 volts. Therefore

$V_E = V_B+V_{BE}$

$V_E = 10.2V+0.7V$

$V_E = 10.9V$

The voltage across R_E is the difference between V_EE and V_E.

$V_{R_E} = V_{EE}-V_E$

$V_{R_E} = 15 V-10.9 V$

$V_{R_E} = 4.1V$

This is the same value we arrived at using method one, so the collector current must be the same at 1.24 mA.

To find V_CE we also have options. One path is to use a slightly modified Equation 4.4.4

$V_{CE} = -(V_{EE} -I_C (R_C+R_E ))$

$V_{CE} = -15V +1.24 mA (3.9 k\Omega +3.3 k\Omega )$

$V_{CE} = -6.07V$

The collector is negative relative to the emitter, hence the negative sign. To avoid this, we could just swap the leads and refer to V_EC instead.

Alternately, we could find V_CE by determining V_C and then subtracting V_E from it.

$V_C = I_C R_C$

$V_C = 1.24 mA\times 3.9 k\Omega$

$V_C = 4.84 V$

$V_{CE} = V_C-V_E$

$V_{CE} = 4.84 V-10.9 V$

$V_{CE} = -6.06V$

We see a very slight difference here due to carried rounding errors.

It is instructive to compare the results of Example 4.4.2 back to Example 4.4.1. These circuits are otherwise identical except for the fact that one is NPN and the other is PNP. We find the same results for device currents (I_C ) and component voltage magnitudes (V_CE or the voltage across R_E); only the signs and directions are reversed. On the other hand, we find that ground referenced potentials such as V_B, V_C and V_E are decidedly different between the two circuits.

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Semiconductor Devices: Theory and Application Copyright © 2023 by James M. Fiore is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License, except where otherwise noted.

Verification of Stability

PNP Voltage Divider Bias

Method One

Method Two

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