25 JFET Amplifiers

Theory Overview

In many regards, JFET amplifiers share similar attributes with their bipolar counterparts. Superficially, they look very similar as well. The main functional differences are that JFET based amplifiers tend to have higher input impedances but tend to offer lower voltage gains. Further, without swamping, JFET amplifiers tend to produce lower levels of distortion. As with r’e impacting bipolar circuit performance, JFET performance is impacted by the transconductance, gm (AKA gfs). Like the bipolar common emitter amplifier, the common source amplifier exhibits a voltage gain greater than one with inversion. The source follower, like the bipolar emitter follower, shows a voltage gain just under one with no inversion.

Equipment

Schematics

Procedure

Common Source Voltage Amplifier

1. Consider the circuit of Figure 1 using Vdd = 15 volts, Vss = −3 volts, Rin = 33 kΩ, Rg = 330 kΩ, Rs = 4.7 kΩ, Rd = 4.7 kΩ, Rload = 22 kΩ, Cin = Cout = 10 µF and Cs = 470 µF. Assuming VGS = −2 volts and gm = 2 mS (4 mS if using the J112), determine the theoretical gain and input impedance of the circuit and record these in Table 1.
2. Build the circuit of Figure 1 using Vdd = 15 volts, Vss = −3 volts, Rin = 33 kΩ, Rg = 330 kΩ, Rs=4.7 kΩ, Rd = 4.7 kΩ, Rload = 22 kΩ, Cin = Cout = 10 µF and Cs = 470 µF. Set Vin to a 100 mV peak sine at 1 kHz. Measure the voltages at the gate and load, and record these in Table 1. Capture images of the input and gate voltages, and the gate and load voltages. Note whether or not the load is inverted compared to the gate signal.
3. Based on the measured gate and drain voltages, determine the resulting theoretical Av and Zin, and record these in Table 1. Note that Zin may be computed using the voltage divider rule or Ohm’s law given the gate and input voltages along with the input resistor value. Also determine and record the percent deviations.
4. Repeat steps 1 through 3 for the remaining two JFETs.

Common Drain Voltage Follower

5. Consider the circuit of Figure 2 using Vdd = 15 volts, Vss = −3 volts, Rin = 33 kΩ, Rg = 330 kΩ, Rs = 4.7 kΩ, Rload = 22 kΩ, Cin = 10 µF and Cout = 470 µF. Assuming VGS = −2 volts and gm = 2 mS (4 mS if using the J112), determine the theoretical gain and input impedance of the circuit and record in Table 2.
6. Build the circuit of Figure 2 using Vdd = 15 volts, Vss = −3 volts, Rin = 33 kΩ, Rg = 330 kΩ, Rs=4.7 kΩ, Rload = 22 kΩ, Cin = 10 µF and Cout = 470 µF. Set Vin to a 100 mV peak sine at 1 kHz. Measure the voltages at the gate and load, and record these in Table 2. Capture images of the input and gate voltages, and the gate and load voltages. Note whether or not the load is inverted compared to the gate signal.
7. Based on the measured gate and drain voltages, determine the resulting theoretical Av and Zin, and record these in Table 2. Also determine and record the percent deviations.
8. Repeat steps 5 through 7 for the remaining two JFETs.

Troubleshooting

9. Consider each of the individual faults listed in Table 3 and estimate the resulting AC load voltage for circuit 1. Introduce each of the individual faults in turn and measure and record the load voltage in Table 3.

Data Tables