2.2 Simplified AC Model of the JFET

An AC model of the JFET is shown in Figure 11.2.1. This is essentially the same model as was used for DC analysis. Once again, we have a voltage-controlled current source situated in the drain. The reverse-biased junction shows up as a very large resistance, 𝑟_𝐺𝑆.

It is worth mentioning that this model is suitable only for low frequencies. At higher frequencies, device capacitances can play a major role in the response of the amplifier. There are three device capacitances not shown in the Figure that shunt each pair of terminals: 𝐶_𝐺𝑆, 𝐶_𝐷𝐺 and 𝐶_𝐷𝑆. On a data sheet, the “lumped” capacitances are often given. These are 𝐶_𝑖𝑠𝑠, the capacitance looking into the gate with the source and drain shorted to ground: 𝐶𝑖𝑠𝑠=𝐶𝐺𝑆+𝐶𝐷𝐺; and 𝐶𝑟𝑠𝑠, the capacitance seen from the drain with the gate and source shorted to ground: 𝐶_𝑟𝑠𝑠=𝐶_𝐷𝑆+𝐶_𝐷𝐺. As we shall see, these capacitances can have a sizable impact on amplifier characteristics such as 𝑍_𝑖𝑛.

The value of transconductance, 𝑔_𝑚, will prove to be of particular interest. It is roughly of equal importance to 𝑟′_𝑒 in a BJT.^[1]