# 4.2 MOSFET Common Source Amplifiers

Before we can examine the common source amplifier, an AC model is needed for both the DE- and E-MOSFET. A simplified model consists of a voltage-controlled current source and an input resistance, ππΊπ. This model is shown in Figure 4.2.1 . The model is essentially the same as that used for the JFET. Technically, the gate-source resistance is higher in the MOSFET due to the insulated gate, and this is useful in specific applications such as in the design of electrometers, but for general purpose work it is a minor distinction. The impedance associated with the current source is not shown as it is typically large enough to ignore. Similarly, the device capacitances are not shown. It is worth noting that the capacitances associated with small signal devices might be just a few picofarads, however, a power device might exhibit values of a few nanofarads.

As the device model is the same for both DE- and E-MOSFETs, the analysis of voltage gain, input impedance and output impedance will apply to both devices. The only practical differences will be how the transconductance is determined, and circuit variations due to the differing biasing requirements which will effect the input impedance. In fact, there will be a great uniformity between JFET-based circuits and DE-MOSFET circuits operating in depletion mode.

An AC equivalent of a swamped common source amplifier is shown in Figure 4.2.2 . This is a generic prototype and is suitable for any variation on device and bias type. Ultimately, all of the amplifiers can be reduced down to this equivalent, occasionally with some resistance values left out (either opened or shorted). For example, if the amplifier is not swamped then ππ=0 . Similarly, ππΊ might correspond to a single gate biasing resistor or it might represent the equivalent of a pair of resistors that set up a gate voltage divider.

## Voltage Gain

In order to derive an equation for the voltage gain, we start with its definition, namely that voltage gain is the ratio of π£ππ’π‘ to π£ππ. We then proceed by expressing these voltages in terms of their Ohm’s law equivalents. Note that ππΏ can also be called ππ·.

(4.2.1)

or, if preferred

(4.2.2)

This is the general equation for voltage gain. If the amplifier is not swamped then the first portion of the denominator drops out and the gain simplifies to

(4.2.3)

or alternately

(4.2.4)

The swamping resistor, ππ, plays the same role here as it did with both the BJT and JFET. Swamping helps to stabilize the gain and reduce distortion, but at the expense of voltage gain.

## Input Impedance

Referring back to Figure 4.2.2 , the input impedance of the amplifier will be ππΊ in parallel with the impedance looking into the gate terminal, πππ(πππ‘π). At a minimum this will be ππΊπ (it is somewhat higher when swamped but this can be ignored in most cases). At low frequencies ππΊπ is very large, perhaps as high as 1012 ohms. In most practical circuits, ππΊ will be much lower, hence

(4.2.5)

It is important to reiterate that ππΊ is the equivalent resistance seen prior to the gate terminal that is seen from the vantage point of πππ. In the case of self bias, combination bias, zero bias and constant current bias, this will be the single biasing resistor ππΊ. For simple voltage divider biasing, ππΊ will be the parallel combination of the two divider resistors (i.e., π1||π2). For decoupled voltage divider biasing, as shown in Figure 4.2.3 , ππΊ will be the decoupling resistor (i.e., π3 ) that is connected between the divider and the gate. This is because the divider node is bypassed to ground via a capacitor. Finally, for drain feedback biasing, ππΊ is the Millerized ππΊ that bridges the drain and gate.

## Output Impedance

The derivation of output impedance is unchanged from the JFET case. From the perspective of the load, the output impedance will be the drain biasing resistor, ππ·, in parallel with the internal impedance of the current source within the device model. ππ· tends to be much lower than this, and thus, the output impedance can be approximated as ππ·.

Therefore we may state

(4.2.6)

At this point, a variety of examples are in order to illustrate some of the myriad combinations.

Example 4.2.1

For the amplifier in Figure 4.2.4 , determine the input impedance and load voltage. πππ = 20 mV, ππ·π· = 20 V, ππΊ = 1 M Ξ© , ππ· = 1.8 k Ξ© , πππ = 20 Ξ© , ππ = 400 Ξ© , ππΏ = 12 k Ξ© , πΌπ·ππ = 40 mA, ππΊπ(πππ) = β1 V.

This is a swamped common drain amplifier utilizing self bias. πππ can be determined via inspection.

To find the load voltage we’ll need the voltage gain, and to find the gain we’ll first need to find ππ0.

The combined DC value of ππ is 420 Ξ© , therefore ππ0ππ = 33.6. From the self bias equation or graph this produces a drain current of 1.867 mA.

The swamping resistor, ππ , is 20 Ξ© . The voltage gain is

And finally

## Computer Simulation

The amplifier of Example 4.2.1 is simulated to verify the results. The circuit is entered into the simulator as shown in Figure 4.2.5 . One issue is finding an appropriate DE-MOS device to match the parameters used in the example. The BSS229 proves to be reasonably close. This device model was tested for πΌπ·ππ by applying a 20 volt source to the drain and shorting the source and gate terminals to ground in the simulator. The current was just under the 40 mA target. Similarly, a negative voltage was attached to the gate and adjusted until the drain current dropped to nearly zero in order to determine ππΊπ(πππ) . The model’s value was just under the desired β1 volt. Consequently, we can expect the simulation results to be close to those predicted, although not identical.

The transient analysis is run next and is shown in Figure 4.2.6 . The expected signal inversion is obvious. The peak amplitude is 417 mV, just a few percent higher than the calculated value. At least some of this deviation is due to the model’s variation from the assumed device parameter values.

A DC bias check is also performed. The drain current was calculated to be 1.867 mA. This yields an ππ· voltage of a little over 3 volts, thus we expect to see a drain voltage of about 17 volts. Similarly, we would expect the source terminal to be sitting at around 700 to 800 mV and the gate at about 0 V.

The results of the DC operating point simulation are shown in Figure 4.2.7 . The agreement with the predicted values is quite good, especially considering that the device model is not a perfect match.

Example 4.2.2

For the circuit of Figure 4.2.8 , determine the voltage gain and input impedance. Assume ππΊπ(π‘β) = 2 V, πΌπ·(ππ) = 50 mA at ππΊπ(ππ) = 5 V.

First find the value of π :

This circuit uses power supply decoupling. The voltage drop across the 2 M Ξ© resistor is small enough to ignore as the current passing through it is gate current. Therefore the gate voltage is determined by the divider. Also, as the left end of the 2 M Ξ© resistor is tied to an AC ground due to the bypass capacitor, it represents the input impedance.

The source is grounded so ππΊπ=ππΊ .

This amplifier is not swamped so the simplified gain equation may be used.

Example 4.2.3

For the circuit of Figure 4.2.9 , determine the voltage gain and input impedance. Assume ππΊπ(πππ) = β0.75 V and πΌπ·ππ = 6 mA.

This amplifier uses zero bias, therefore πΌπ·=πΌπ·ππ and ππ=ππ0 .

This amplifier is not swamped so we may use the simplified equation for voltage gain.

Finally, for the input impedance we have