# 1.4 JFET Biasing

There are several different ways of biasing a JFET. For many configurations, πΌ_{π·ππ} and π_{πΊπ(πππ}) will be needed. A simple way to measure these parameters in the lab is shown in Figure 1.4.1. To measure πΌ_{π·ππ} we simply ground the gate and source terminals as this forces π_{πΊπ} to be 0 V. We insert an ammeter between π_{π·π·} and the drain, and then set π_{π·π·} to a value higher than π_{π} (+15 V_{DC} generally being sufficient). The resulting ammeter reading is πΌ_{π·ππ}. Obtaining π_{πΊπ(πππ)} is only slightly more work. Leaving the ammeter in the drain, unhook the gate from ground and instead connect it to an adjustable negative power supply. Turn the supply more negative until the ammeter reads zero (practically speaking, < 1% of πΌ_{π·ππ}). At that point the voltage source will be equal to π_{πΊπ(πππ).}

## DC Model

Before we begin examining the bias circuits themselves, we need a basic DC model of the JFET. A model sufficient for our analyses is shown in Figure 1.4.2.

The model consists of a voltage-controlled current source, πΌ_{π·}, that is equal to the product of the gate-source voltage, π_{πΊπ}, and the transconductance, π_{π}. The resistance between the gate and source, π
_{πΊπ}, is that of the reverse-biased P_{N} junction, in other words, ideally infinity for DC. As a consequence, in most practical circuits we can assume that gate current, πΌ_{πΊ}, is zero. Therefore, πΌ_{π·}=πΌ_{π}.

## Constant Voltage Bias

The simplest form of bias is the constant voltage bias. The prototype is shown in Figure 1.4.3 with current directions and voltage polarities shown.

This is a fairly straightforward design using only a couple of resistors and power sources. Figure 1.4.4 shows the same circuit but with the JFET model inserted, ready for analysis.

Ultimately, the goal here is to determine a means for finding the transistor’s drain current and drain-source voltage, along with the potentials across any other components.

To begin, consider the gate-source loop. By KVL, the π_{πΊπΊ }source must drop across π
_{πΊ} and the gate-source junction, π_{πΊπ}.

πΌ_{πΊ} is approximately zero so this simplifies to

Given the transconductance, ππgm, we can find πΌ_{π·}. Alternately, πΌ_{π·} may be found using Equation 1.2.1 along with the device parameters πΌ_{π·ππ} and π_{πΊπ(πππ)}. For this circuit, the latter technique tends to be more practical. Once πΌ_{π·} is found, the voltage drop across π
_{π·} may be found, and then π_{π·π} is determined from KVL.

Example 1.4.1

For the circuit of Figure 1.4.5, determine πΌ_{π·} and π_{π·π}. Assume πΌ_{π·ππ} = 10 mA and π_{πΊπ(πππ)} = β5 V.

First, because πΌ_{πΊ}β0, the drop across π
_{πΊ} is β0 and π_{πΊπ}=π_{πΊπΊ}. Using Equation 1.2.1

Looking at the drain-source loop, KVL shows

While the computation for the constant voltage bias is relatively simple, it does not exhibit a stable Q point. For example, if Example 1.4.1 is repeated with another JFET, this one with πΌ_{π·ππ} = 12 mA and π_{πΊπ(πππ)} = β6 V, the results are starkly different: πΌ_{π·} grows to 5.33 mA and π_{π·π} shrinks to 7.4 V. These are considerable changes given the relatively modest shifts in the device parameters. In this regard, the constant voltage bias is reminiscent of the simple base bias configuration used with BJTs.

To get a better understanding of the Q point stability issue, refer to Figure 1.4.6.

Characteristic curves are plotted here for two different devices, one in green and one in blue. These represent the sort of device parameter variations we might expect to see across a product model. The fixed value of gate bias voltage is shown in red. From this graph it should be obvious that this form of bias will produce a wide variation in drain current, and thus, is not a good choice for applications that require a stable Q point. If the application does not have this requirement, constant voltage bias offers the advantage of requiring a minimum of components.

## Self Bias

Self bias uses a small number of components and only a single power supply, yet it offers better stability than constant voltage bias. The name comes from the fact that the drain current will be used to create a voltage drop that sets up the gate-source, hence the circuit βbiases itselfβ. It is also referred to as automatic bias. The self bias prototype is shown in Figure 1.4.7.

Once again, we may assume that πΌ_{πΊ} is 0. As π
_{πΊ} is connected directly to ground, this means that π_{πΊ}β0. This being true, inspection of the schematic reveals that the magnitude of π_{πΊπ} must be the same as the voltage across π
_{π}. Because πΌ_{π·}=πΌ_{π} then

(1.4.1)

This value of π_{πΊπ} is what generates the drain current. The definition is self-referential. This being the case, how do we analyze the circuit? A proper derivation of the equation for drain current is not trivial. We start with the characteristic equation (Equation 11.2.1) and expand it.

Substitute using Equation 1.2.2

Using Equation 1.4.1 this can be expanded to

Rearranging yields

This is a quadratic equation in the formΒ ππ₯^{2}+ππ₯+πax^{2}+bx+cΒ and can be solved using the quadratic formula:

The positive option in the numerator may be ignored as this occurs or π_{πΊπ} beyond π_{πΊπ(πππ)}. The result is

(1.4.2)

Although this is an accurate analytical solution, it’s certainly not the sort of equation most people want to memorize or derive as needed. As the π_{π0π
π} term is repeated in this equation multiple times, it is useful to plot this equation in terms of normalized πΌ_{π·} versus π_{π0π
π}. This curve is plotted in Figure 1.4.8.

The value of π_{π0π
π} is found on the horizontal axis, traced up to the curve and then over to the normalized πΌ_{π·} ratio. This number is multiplied by πΌ_{π·ππ} to determine the value of πΌ_{π·}.

Example 1.4.2

Determine πΌ_{π·} and π_{π·π} for the circuit shown in Figure 11.4.9. Assume πΌ_{π·ππ} = 10 mA and π_{πΊπ(πππ)} = β4 V.

Using the graphical method, first determine π_{π0π
π}.

Therefore π_{π0π
π} = 5 mS β
2.2 k Ξ©=11. The self bias graph yields approximately 0.12 for the normalized current ratio. Therefore

Using Ohm’s law and KVL

An alternate technique is to make an initial guess for π_{πΊπ}, typically one half of π_{πΊπ(πππ)}. The value of πΌ_{π·} is then computed from the characteristic equation (Equation 1.2.1) and compared with the Ohm’s law relation, Equation 1.4.1, rewritten as πΌ_{π·}=βπ_{πΊπ}/π
_{π}. Chances are, the two results will not agree so adjust the π_{πΊπ} estimate and repeat the process. If done properly, the currents should be closer. Iterate this process until you converge on the answer.

To use this technique for the preceding problem we’d start by assuming π_{πΊπ} = β2 V (half of π_{πΊπ(πππ))}). Using this in Equation 1.2.1 yields πΌ_{π·} = 2.5 mA, while using Equation 1.4.1 produces πΌ_{π·} = 910 πA. Obviously the initial estimate was not correct. The second estimate for ππΊπVGS needs to increase negatively as this will decrease the result from Equation 1.2.1 and increase the result from Equation 1.4.1, hopefully meeting in the middle. We might try β2.5 volts. This will yield 1.4 mA from Equation 1.2.1 and 1.14 mA from Equation 1.4.1. As the gap has narrowed, the adjustment for the third estimate will be smaller, so we could try β2.6 volts. This would be relatively close to the value as computed in Example 1.4.2 (π_{πΊπ}=βπ_{π}).

This approximation technique also offers a clue as to how self bias gains stability over constant voltage bias. If for some reason πΌ_{π·} was to increase, this would create a larger voltage drop across π
_{π}. Because this voltage is the same magnitude as π_{πΊπ}, this means that π_{πΊπ} grows negatively. A more negative π_{πΊπ} reduces πΌ_{π·}, thus opposing the initial change in drain current. This feedback mechanism is similar in function to the BJT collector feedback bias. The stability issue is visualized in Figure 1.4.1.

Two device curves are plotted to represent parameter variation (green and blue). Equation 1.4.1 shows the relationship between πΌ_{π·} and π_{πΊπ}. If we put this in the form π¦=ππ₯+πy=mx+b, we find that the line goes through the origin and has a slope of 1/π
_{π}. This line is plotted in red. Where the line intersects the device curve yields the drain current and gate-source voltage for that particular device. Unlike constant voltage bias, self bias shifts some variation over to π_{πΊπ}, making πΌ_{π·} more stable. In fact, if there is a particular design target for πΌ_{π·} or π_{πΊπ,} a rearrangement of Equation 1.4.1 can be used to find the needed value of π
_{π} along with the characteristic curve or equation.

For example, if a certain πΌ_{π·} is desired, this value could be used with Equation 1.2.1 to determine the corresponding π_{πΊπ}. These values are then used to find the required π
_{π}. Alternately, the normalized values could be obtained via Figure 11.2.4.

Example 1.4.3

Determine a value for π
_{π} to set π_{πΊπ} = β2 V for the circuit shown in Figure 1.4.11. Assume πΌ_{π·ππ}= 20 mA and π_{πΊπ(πππ)} = β4 V.

We can determine the drain current using Equation 1.2.1.

In sum, self bias is a minimal parts count circuit that offers modest stability. The stability can be improved with the addition of other components, as we shall see with the next bias configuration.

## Combination Bias

The combination bias configuration (AKA source bias) is based on self bias but adds a negative power supply connected to π
_{π}, hence its name. This will enhance the stability of πΌ_{π·}, π_{π·π} and π_{π}. The combination bias prototype is shown in Figure 1.4.12.

The analysis is similar to that of self bias but with one major twist: the source power supply increases the voltage drop across π
_{π}. This stabilizes the voltage (and hence, the current) because it is no longer equal to βπ_{πΊπ}, but rather

(1.4.3)

If π_{ππ}β«π_{πΊπ}, then we can approximate πΌ_{π·} as π_{ππ}/π
_{π}. As with self bias, an analytical solution for πΌ_{π·} is possible. In order to do so, we would begin with the characteristic equation and Equation 1.4.3. The derivation is left as an exercise.

(1.4.4)

The formula is very similar to the self bias formula but with the addition of a factor, π. π is a βswamping factorβ and is defined as the ratio of π_{ππ} to π_{πΊπ(πππ)}. If π=0, there is no source power supply and the formula reverts back to the simpler self bias formula. On the other hand, if π is very large, πΌ_{π·}βπ_{ππ}/π
_{π}.

As was the case with self bias, we can plot Equation 1.4.4 using the π_{π0π
π} factor. A series of three plots for π = 2, 3 and 4 are rendered in Figure 1.4.13.^{[1]}

Example 1.4.4

Determine πΌ_{π·} and π_{π·π} for the circuit shown in Figure 1.4.14. Assume πΌ_{π·ππ} = 12 mA and π_{πΊπ(πππ)} = β4 V.

Using the graphical method, first determine π_{π0π
π}.

Therefore π_{π0π
π} = 6 mS β
3.3 k Ξ© = 19.8. The swamping ratio, π, is π_{ππ}/π_{πΊπ(πππ)}=β8/β4=2. This requires the graph in Figure 1.4.13π. This graph yields approximately 0.25 for the normalized current ratio. Therefore

Using Ohm’s law and KVL

As a crosscheck, using Equation 1.4.4 yields 3.028 mA for πΌ_{π·}. The deviation is no doubt due to inaccuracy in reading the graph. In any case, using this value of drain current we find π_{π} to be 1.992 volts, a little higher than calculated above. This indicates that π_{πΊπ} is β1.992 volts (because π_{πΊ}β0). If we plug this value of π_{πΊπ} into Equation 1.2.1, πΌ_{π·}=3.024 mA; an excellent match with the deviation being due to accumulated rounding errors.

In order to show the increased Q point stability of the combination bias, we’ll repeat the preceding problem using a JFET with a significantly lower πΌ_{π·ππ}.

Example 1.4.5

Determine πΌ_{π·} for the circuit shown in Figure 1.4.14. Assume πΌ_{π·ππ} = 8 mA and π_{πΊπ(πππ)} = β4 V.

For this version we’ll use Equation 1.4.4. First determine π_{π0}π
_{π}.

Therefore π_{π0}π
_{π} = 4 mS β
3.3 k Ξ©=13.2. The swamping ratio, π, is π_{ππ}/π_{πΊπ(πππ)}=β8/β4=2.

For the graphical method, a reasonable estimate for the normalized πΌ_{π·} would be around 0.36, yielding a drain current of 2.88 mA. Stability is apparent because the drain current has dropped only a few percent in spite of the fact that πΌ_{π·ππ} decreased by 33%.

The graph of Figure 1.4.15 illustrates nicely the increased stability of the Q point. Once again, we plot two representative device curves in green and blue. As was the case with self bias, a plot line can be drawn, the slope of which is equal to the reciprocal of π
_{π}. This plot line does not go though the origin, though. Instead, the π₯x axis intercept is the voltage |π_{ππ}|. Thus, the red plot line is shifted along the π_{πΊπ} axis.

As can be seen in the graph, the variation in πΌ_{π·} is reduced (although at the expense of variation in π_{πΊπ}). For large values of π_{ππ} with correspondingly large values of π
_{π}, the bias plot line becomes nearly horizontal, indicating a very stable Q point. With two variables in play, this bias proves to be very flexible. It can also be realized by using a positive voltage divider at the gate and removing π_{ππ} (returning π
_{π} to ground).

## Constant Current Bias

The most stable bias for JFETs relies, oddly enough, on a current source made with a BJT. It is called constant current bias, yet another imaginative tag. Interestingly, although this will keep the Q point very stable, a fixed πΌ_{π·} does not guarantee the most stable value of voltage gain. In fact, it might be easier to achieve that goal using combination bias. The prototype constant current bias circuit is shown in Figure 1.4.16. An NPN BJT is used for an N-channel JFET and a PNP would be used with a P-channel JFET, typically driven from above (i.e., circuit flipped top to bottom).

Ignoring the JFET for a moment, the BJT is configured as in two-supply emitter bias. In this case the base is tied directly to ground, leaving the emitter at about β0.7 VDC. The remainder of the π_{πΈπΈ} supply drops across π
_{πΈ}, establishing the emitter current. As the collector is connected directly to the JFET’s source terminal, this means that πΌ_{π}βπΌ_{πΈ}. The source current winds up being just as stable as the emitter current, which we have already seen is very stable. The only requirement is that πΌ_{πΈ} should not be programmed to be larger than πΌ_{π·ππ}. This being true, πΌ_{π·} will set up a corresponding π_{πΊπ}. This also establishes π_{π} because π_{πΊ}β0. Therefore, the source terminal will be a small positive voltage and this is precisely what the BJT needs in order to guarantee that its collector-base junction is reverse-biased.

Computation of circuit currents and voltages is straightforward and does not involve the use of graphical aides. The first step is to examine the BJT’s emitter loop and determine πΌ_{πΈ}. Once this is found, πΌ_{π} and πΌ_{π·} are known, and all remaining component potentials may be found using Ohm’s law and KVL.

This technique does not involve the calculation of π_{πΊπ}. In fact, because πΌ_{π·} is very stable, π_{πΊπ} will show the widest variation of all biasing circuits when the JFET is changed. If π_{πΊπ} is needed, it can be determined via a little algebraic manipulation on Equation 1.2.1.

Example 1.4.6

Determine πΌ_{π·}, π_{π·π} and π_{πΊπ} in the circuit of Figure 1.4.17. πΌ_{π·ππ} = 15 mA and π_{πΊπ(πππ)} = β3 V.

We begin by finding πΌ_{πΈ}.

πΌ_{πΈ} is the same as πΌ_{π} and πΌ_{π·}, therefore

To find π_{π} we note that π_{π}=βπ_{πΊπ} and rearrange Equation 1.2.1.

Therefore π_{π}=1.24V and

We turn next to a computer simulation of a similar circuit to validate our methodology.

## Computer Simulation

A constant current bias circuit is entered into a simulator as shown in Figure 1.4.18.

A cursory estimate shows that πΌ_{πΈ} and πΌ_{π·} should be around 4.3 mA. Also, π_{π·} should be approximately 20 V β 4.3 mA β
2.2 kΞ©, or about 1.54 volts. The results of a DC operating point analysis are shown in Figure 1.4.19.

The drain voltage (node 3) is just over 1.6 volts, agreeing with our estimate. Also, note the minuscule gate voltage (node 1) of 12 πV which verifies our continuing assumption in these circuits that π_{πΊ}β0 V_{DC}. Finally, we see a modest potential of about 1.5 volts at the source terminal (node 12). This shows the proper reverse-biasing of both the gate-source and collector-base junctions.

Finally, we can examine the Q point variation using Figure 1.4.20. Here, the plot line is perfectly horizontal and all device variation is manifest in π_{πΊπ}.

- We could add a third axis for π and plot a surface, and while it might be pretty, a 3D plot like this rendered onto a 2D surface, such as a page in a textbook, is of marginal utility. ↵