# 10.6 Problems

## Review Questions

1. What forms of feedback are used for the inverting and noninverting voltage amplifiers?
2. What forms of feedback are used for the current-to-voltage and voltage-to-current transducers?
3. What form of feedback is used for the inverting current amplifier?
4. What are the op amp analysis idealizations?
5. What is virtual ground?
6. What is a summing amplifier?
7. How can output current by increased?
8. What circuit changes are needed in order to bias an op amp with a unipolar supply?
9. What operational parameters change when a circuit is set up for single supply biasing?
10. How might a circuit’s gain be controlled externally?
11. What is meant by the term βfloating loadβ?

## Problems

### Analysis Problems

1. What is the voltage gain in Figure 4.6.1 ? What is the input impedance?
2. What is the voltage gain for the first stage of Figure 4.6.2 ? What is the input impedance?
3. What is the voltage gain for the second stage of Figure 4.6.2 ? What is the input impedance?
4. What is the system voltage gain in FigureΒ 4.6.24.6.2? What is the input impedance?
5. If the input to Figure 4.6.2 is -52 dBV, what is πβ²ππ’π‘ ?
6. What is the voltage gain in Figure 4.6.3? What is the input impedance?
7. If the input voltage to the circuit of Figure 4.6.3 is 100 mV, what is πππ’π‘?
8. What is the system input impedance in Figure 4.6.4 ? What is the system gain?
9. Redesign Figure 4.6.4 for an input impedance of 20 k Ξ© .
10. Given an input current of 2 π A, what is the output voltage in Figure 4.6.5 ?
11. What is the meter deflection in Figure 4.6.6 if the input voltage is 1 V?
12. What input voltage will produce full-scale deflection in figure 4.6.6 ?
13. Determine a new value for the 10 k Ξ© resistor in Figure 4.6.6 such that a 0.1 V input will produce full-scale deflection.
14. What is the current gain in Figure 4.6.7 ?
15. What is the maximum input current in Figure 4.6.7 , assuming the circuit is running off of Β± 15 V supplies, and the op amp has a maximum output current of 25 mA?
16. If the differential input signal is 300 mV in Figure 4.6.8 , what is πππ’π‘?
17. Determine new values for the voltage divider resistors in Figure 4.6.8 , such that the resulting input impedance is balanced.

### Design Problems

1. Design a noninverting amplifier with a voltage gain of 32 dB and an input impedance of 200 k Ξ©.
2. Design a voltage follower with a gain of 0 dB.
3. Design an inverting amplifier with a voltage gain of 14 dB and an input impedance of 15 k Ξ©.
4. Design a current-to-voltage transducer such that a 20 π A input current will produce a -1 V output.
5. Design a voltage-to-current transducer such that a 100 mV input will produce a 1 mA output.
6. Design a current amplifier with a gain of -20.
7. Design a differential amplifier with a gain of 18 dB and a balanced input impedance of 25 k Ξ© per input.
8. Design a voltage to current transducer with a transconductance of 1 mS. If πππis 200 mV, what is πΌππ’π‘ ?
9. Design a current to voltage transducer with a transresistance of 10 k Ξ© . If the input current is 500 π A, what is πππ’π‘?
10. Redesign the circuit of Figure 4.6.1 for single supply operation (don’t bother calculating capacitor values).
11. Redesign the circuit of Figure 4.6.3 for single supply operation (don’t bother calculating capacitor values).
12. Design a summing amplifier such that channel 1 has a gain of 10, channel 2 has a gain of 15, and channel 3 has a gain of 5. The minimum channel input impedance should be 1 k Ξ© .
13. Determine capacitor values for Problem 27 if the lower break frequency π1 , is set to 20 Hz.
14. Determine capacitor values for Problem 28 if the lower break frequency f1, is set to 10 Hz.

### Challenge Problems

1. Design a three channel summing amplifier such that: channel 1 πππβ₯10πΞ© , π΄π£ = 6 dB; channel 2 πππβ₯22πΞ© , π΄π£ = 10 dB; and channel 3 πππβ₯5πΞ© , π΄π£ = 16 dB
2. Assuming 10% resistor values, determine the production gain range for Figure 4.6.1 .
3. Assuming 5% resistor values, determine the highest gain produced in Figure 4.6.2 .
4. Design an inverting amplification circuit with a gain of at least 40 dB, and an input impedance of at least 100 k Ξ© . No resistor used may be greater than 500 k Ξ© . Multiple stages are allowed.
5. Redesign the circuit of Figure 4.6.3 as a voltmeter with 500 mV, 2 V, 5 V, 20 V, and 50 V ranges.
6. Assuming 1% precision resistors and a meter accuracy of 5%, what range of input values may produce a full-scale reading of 2 V, for the circuit of Problem 36?
7. Design an amplifier with a gain range from -10 dB to +20 dB, with an input impedance of at least 10 k Ξ© .
8. Design an amplifier with a gain range from 0 to 20. The input impedance should be at least 5 k Ξ© .
9. What is the input impedance in Figure 4.6.9 ? What is π΄π£ ?
10. How much power supply ripple attenuation does the input biasing network of Figure 4.6.9 produce (assume πππππππ = 120 Hz)?
11. Assume that the circuit of Figure 4.6.10 utilizes a standard 20 mA output op amp. If the output devices are rated for a maximum collector current of 5 amps and a Beta of 50, what is the maximum load current obtainable?
12. What are the voltage gain and input impedance in Figure 4.6.10 ?
13. Given a summer based on Figure 4.2.22, sketch the output waveform if π1=π2= 10 k Ξ© , π3=ππ= 30 k Ξ© , ππ = 15 k Ξ© , π1 = 0.3 V DC, π2=0.1sin2π50π‘ and π3=β0.2sin2π200π‘ .
14. Prove Equation 4.2.15 for the case when all resistors are of equal value.

### Computer Simulation Problems

1. Simulate the operation of the circuit in Figure 4.2.9. Verify the output voltage and the virtual ground at the inverting input.
2. Use a simulator to verify the maximum and minimum gains of the circuit in Figure 4.2.11.
3. Use a simulator to verify the load current and the voltage of the circuit in Figure 4.2.17.
4. Verify the output potential of the circuit in Figure 4.2.20.
5. Simulate the output voltage of the circuit of Figure 4.6.4 for the following inputs:
1. πππ=0.1 VDC,
2. πππ(π‘)=1sin2π10π‘,
3. πππ=5 VDC.

Also, note the potential at the output of the first stage. How might your op amp model affect the results?

6. Simulate the circuit in Figure 4.2.27. Determine the output potential for the following inputs:
1. πππ+(π‘)=0.1sin2π10π‘ , πππβ(π‘)=0.1sin2π10π‘,
2. πππ+(π‘)=0.1sin2π10π‘ , πππβ(π‘)=β0.1sin2π10π‘.
7. Simulate the circuit of Figure 4.6.10 , and determine the output of the circuit and op amp for inputs of 0.1 V DC and 1 V DC.

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