1.4 JFET Biasing

There are several different ways of biasing a JFET. For many configurations, 𝐼_𝐷𝑆𝑆 and 𝑉_{𝐺𝑆(𝑜𝑓𝑓}) will be needed. A simple way to measure these parameters in the lab is shown in Figure 1.4.1. To measure 𝐼_𝐷𝑆𝑆 we simply ground the gate and source terminals as this forces 𝑉_𝐺𝑆 to be 0 V. We insert an ammeter between 𝑉_𝐷𝐷 and the drain, and then set 𝑉_𝐷𝐷 to a value higher than 𝑉_𝑃 (+15 V_DC generally being sufficient). The resulting ammeter reading is 𝐼_𝐷𝑆𝑆. Obtaining 𝑉_{𝐺𝑆(𝑜𝑓𝑓)} is only slightly more work. Leaving the ammeter in the drain, unhook the gate from ground and instead connect it to an adjustable negative power supply. Turn the supply more negative until the ammeter reads zero (practically speaking, < 1% of 𝐼_𝐷𝑆𝑆). At that point the voltage source will be equal to 𝑉_{𝐺𝑆(𝑜𝑓𝑓).}

DC Model

Before we begin examining the bias circuits themselves, we need a basic DC model of the JFET. A model sufficient for our analyses is shown in Figure 1.4.2.

The model consists of a voltage-controlled current source, 𝐼_𝐷, that is equal to the product of the gate-source voltage, 𝑉_𝐺𝑆, and the transconductance, 𝑔_𝑚. The resistance between the gate and source, 𝑅_𝐺𝑆, is that of the reverse-biased P_N junction, in other words, ideally infinity for DC. As a consequence, in most practical circuits we can assume that gate current, 𝐼_𝐺, is zero. Therefore, 𝐼_𝐷=𝐼_𝑆.

Constant Voltage Bias

The simplest form of bias is the constant voltage bias. The prototype is shown in Figure 1.4.3 with current directions and voltage polarities shown.

This is a fairly straightforward design using only a couple of resistors and power sources. Figure 1.4.4 shows the same circuit but with the JFET model inserted, ready for analysis.

Ultimately, the goal here is to determine a means for finding the transistor’s drain current and drain-source voltage, along with the potentials across any other components.

To begin, consider the gate-source loop. By KVL, the 𝑉_𝐺𝐺 source must drop across 𝑅_𝐺 and the gate-source junction, 𝑉_𝐺𝑆.

𝐼_𝐺 is approximately zero so this simplifies to

Given the transconductance, 𝑔𝑚gm, we can find 𝐼_𝐷. Alternately, 𝐼_𝐷 may be found using Equation 1.2.1 along with the device parameters 𝐼_𝐷𝑆𝑆 and 𝑉_{𝐺𝑆(𝑜𝑓𝑓)}. For this circuit, the latter technique tends to be more practical. Once 𝐼_𝐷 is found, the voltage drop across 𝑅_𝐷 may be found, and then 𝑉_𝐷𝑆 is determined from KVL.

Example 1.4.1

For the circuit of Figure 1.4.5, determine 𝐼_𝐷 and 𝑉_𝐷𝑆. Assume 𝐼_𝐷𝑆𝑆 = 10 mA and 𝑉_{𝐺𝑆(𝑜𝑓𝑓)} = −5 V.

First, because 𝐼_𝐺≈0, the drop across 𝑅_𝐺 is ≈0 and 𝑉_𝐺𝑆=𝑉_𝐺𝐺. Using Equation 1.2.1

   

   

   

Looking at the drain-source loop, KVL shows

   

   

   

   

While the computation for the constant voltage bias is relatively simple, it does not exhibit a stable Q point. For example, if Example 1.4.1 is repeated with another JFET, this one with 𝐼_𝐷𝑆𝑆 = 12 mA and 𝑉_{𝐺𝑆(𝑜𝑓𝑓)} = −6 V, the results are starkly different: 𝐼_𝐷 grows to 5.33 mA and 𝑉_𝐷𝑆 shrinks to 7.4 V. These are considerable changes given the relatively modest shifts in the device parameters. In this regard, the constant voltage bias is reminiscent of the simple base bias configuration used with BJTs.

To get a better understanding of the Q point stability issue, refer to Figure 1.4.6.

Characteristic curves are plotted here for two different devices, one in green and one in blue. These represent the sort of device parameter variations we might expect to see across a product model. The fixed value of gate bias voltage is shown in red. From this graph it should be obvious that this form of bias will produce a wide variation in drain current, and thus, is not a good choice for applications that require a stable Q point. If the application does not have this requirement, constant voltage bias offers the advantage of requiring a minimum of components.

Self Bias

Self bias uses a small number of components and only a single power supply, yet it offers better stability than constant voltage bias. The name comes from the fact that the drain current will be used to create a voltage drop that sets up the gate-source, hence the circuit “biases itself”. It is also referred to as automatic bias. The self bias prototype is shown in Figure 1.4.7.

Once again, we may assume that 𝐼_𝐺 is 0. As 𝑅_𝐺 is connected directly to ground, this means that 𝑉_𝐺≈0. This being true, inspection of the schematic reveals that the magnitude of 𝑉_𝐺𝑆 must be the same as the voltage across 𝑅_𝑆. Because 𝐼_𝐷=𝐼_𝑆 then

(1.4.1)

This value of 𝑉_𝐺𝑆 is what generates the drain current. The definition is self-referential. This being the case, how do we analyze the circuit? A proper derivation of the equation for drain current is not trivial. We start with the characteristic equation (Equation 11.2.1) and expand it.

Substitute using Equation 1.2.2

Using Equation 1.4.1 this can be expanded to

Rearranging yields

This is a quadratic equation in the form 𝑎𝑥²+𝑏𝑥+𝑐ax²+bx+c and can be solved using the quadratic formula:

The positive option in the numerator may be ignored as this occurs or 𝑉_𝐺𝑆 beyond 𝑉_{𝐺𝑆(𝑜𝑓𝑓)}. The result is

(1.4.2)

Although this is an accurate analytical solution, it’s certainly not the sort of equation most people want to memorize or derive as needed. As the 𝑔_{𝑚0𝑅𝑆} term is repeated in this equation multiple times, it is useful to plot this equation in terms of normalized 𝐼_𝐷 versus 𝑔_{𝑚0𝑅𝑆}. This curve is plotted in Figure 1.4.8.

The value of 𝑔_{𝑚0𝑅𝑆} is found on the horizontal axis, traced up to the curve and then over to the normalized 𝐼_𝐷 ratio. This number is multiplied by 𝐼_𝐷𝑆𝑆 to determine the value of 𝐼_𝐷.

Example 1.4.2

Determine 𝐼_𝐷 and 𝑉_𝐷𝑆 for the circuit shown in Figure 11.4.9. Assume 𝐼_𝐷𝑆𝑆 = 10 mA and 𝑉_{𝐺𝑆(𝑜𝑓𝑓)} = −4 V.

Using the graphical method, first determine 𝑔_{𝑚0𝑅𝑆}.

   

   

   

Therefore 𝑔_{𝑚0𝑅𝑆} = 5 mS ⋅ 2.2 k Ω=11. The self bias graph yields approximately 0.12 for the normalized current ratio. Therefore

   

   

   

Using Ohm’s law and KVL

   

   

   

   

   

   

   

   

   

An alternate technique is to make an initial guess for 𝑉_𝐺𝑆, typically one half of 𝑉_{𝐺𝑆(𝑜𝑓𝑓)}. The value of 𝐼_𝐷 is then computed from the characteristic equation (Equation 1.2.1) and compared with the Ohm’s law relation, Equation 1.4.1, rewritten as 𝐼_𝐷=−𝑉_𝐺𝑆/𝑅_𝑆. Chances are, the two results will not agree so adjust the 𝑉_𝐺𝑆 estimate and repeat the process. If done properly, the currents should be closer. Iterate this process until you converge on the answer.

To use this technique for the preceding problem we’d start by assuming 𝑉_𝐺𝑆 = −2 V (half of 𝑉_{𝐺𝑆(𝑜𝑓𝑓))}). Using this in Equation 1.2.1 yields 𝐼_𝐷 = 2.5 mA, while using Equation 1.4.1 produces 𝐼_𝐷 = 910 𝜇A. Obviously the initial estimate was not correct. The second estimate for 𝑉𝐺𝑆VGS needs to increase negatively as this will decrease the result from Equation 1.2.1 and increase the result from Equation 1.4.1, hopefully meeting in the middle. We might try −2.5 volts. This will yield 1.4 mA from Equation 1.2.1 and 1.14 mA from Equation 1.4.1. As the gap has narrowed, the adjustment for the third estimate will be smaller, so we could try −2.6 volts. This would be relatively close to the value as computed in Example 1.4.2 (𝑉_𝐺𝑆=−𝑉_𝑆).

This approximation technique also offers a clue as to how self bias gains stability over constant voltage bias. If for some reason 𝐼_𝐷 was to increase, this would create a larger voltage drop across 𝑅_𝑆. Because this voltage is the same magnitude as 𝑉_𝐺𝑆, this means that 𝑉_𝐺𝑆 grows negatively. A more negative 𝑉_𝐺𝑆 reduces 𝐼_𝐷, thus opposing the initial change in drain current. This feedback mechanism is similar in function to the BJT collector feedback bias. The stability issue is visualized in Figure 1.4.1.

Two device curves are plotted to represent parameter variation (green and blue). Equation 1.4.1 shows the relationship between 𝐼_𝐷 and 𝑉_𝐺𝑆. If we put this in the form 𝑦=𝑚𝑥+𝑏y=mx+b, we find that the line goes through the origin and has a slope of 1/𝑅_𝑆. This line is plotted in red. Where the line intersects the device curve yields the drain current and gate-source voltage for that particular device. Unlike constant voltage bias, self bias shifts some variation over to 𝑉_𝐺𝑆, making 𝐼_𝐷 more stable. In fact, if there is a particular design target for 𝐼_𝐷 or 𝑉_𝐺𝑆, a rearrangement of Equation 1.4.1 can be used to find the needed value of 𝑅_𝑆 along with the characteristic curve or equation.

For example, if a certain 𝐼_𝐷 is desired, this value could be used with Equation 1.2.1 to determine the corresponding 𝑉_𝐺𝑆. These values are then used to find the required 𝑅_𝑆. Alternately, the normalized values could be obtained via Figure 11.2.4.

Example 1.4.3

Determine a value for 𝑅_𝑆 to set 𝑉_𝐺𝑆 = −2 V for the circuit shown in Figure 1.4.11. Assume 𝐼_𝐷𝑆𝑆= 20 mA and 𝑉_{𝐺𝑆(𝑜𝑓𝑓)} = −4 V.

We can determine the drain current using Equation 1.2.1.

   

   

   

   

   

   

In sum, self bias is a minimal parts count circuit that offers modest stability. The stability can be improved with the addition of other components, as we shall see with the next bias configuration.

Combination Bias

The combination bias configuration (AKA source bias) is based on self bias but adds a negative power supply connected to 𝑅_𝑆, hence its name. This will enhance the stability of 𝐼_𝐷, 𝑉_𝐷𝑆 and 𝑔_𝑚. The combination bias prototype is shown in Figure 1.4.12.

The analysis is similar to that of self bias but with one major twist: the source power supply increases the voltage drop across 𝑅_𝑆. This stabilizes the voltage (and hence, the current) because it is no longer equal to −𝑉_𝐺𝑆, but rather

(1.4.3)

If 𝑉_𝑆𝑆≫𝑉_𝐺𝑆, then we can approximate 𝐼_𝐷 as 𝑉_𝑆𝑆/𝑅_𝑆. As with self bias, an analytical solution for 𝐼_𝐷 is possible. In order to do so, we would begin with the characteristic equation and Equation 1.4.3. The derivation is left as an exercise.

(1.4.4)

The formula is very similar to the self bias formula but with the addition of a factor, 𝑘. 𝑘 is a “swamping factor” and is defined as the ratio of 𝑉_𝑆𝑆 to 𝑉_{𝐺𝑆(𝑜𝑓𝑓)}. If 𝑘=0, there is no source power supply and the formula reverts back to the simpler self bias formula. On the other hand, if 𝑘 is very large, 𝐼_𝐷≈𝑉_𝑆𝑆/𝑅_𝑆.

As was the case with self bias, we can plot Equation 1.4.4 using the 𝑔_{𝑚0𝑅𝑆} factor. A series of three plots for 𝑘 = 2, 3 and 4 are rendered in Figure 1.4.13.^[1]

Example 1.4.4

Determine 𝐼_𝐷 and 𝑉_𝐷𝑆 for the circuit shown in Figure 1.4.14. Assume 𝐼_𝐷𝑆𝑆 = 12 mA and 𝑉_{𝐺𝑆(𝑜𝑓𝑓)} = −4 V.

Using the graphical method, first determine 𝑔_{𝑚0𝑅𝑆}.

   

   

   

Therefore 𝑔_{𝑚0𝑅𝑆} = 6 mS ⋅ 3.3 k Ω = 19.8. The swamping ratio, 𝑘, is 𝑉_𝑆𝑆/𝑉_{𝐺𝑆(𝑜𝑓𝑓)}=−8/−4=2. This requires the graph in Figure 1.4.13𝑎. This graph yields approximately 0.25 for the normalized current ratio. Therefore

   

   

   

Using Ohm’s law and KVL

   

   

   

   

   

   

   

   

   

As a crosscheck, using Equation 1.4.4 yields 3.028 mA for 𝐼_𝐷. The deviation is no doubt due to inaccuracy in reading the graph. In any case, using this value of drain current we find 𝑉_𝑆 to be 1.992 volts, a little higher than calculated above. This indicates that 𝑉_𝐺𝑆 is −1.992 volts (because 𝑉_𝐺≈0). If we plug this value of 𝑉_𝐺𝑆 into Equation 1.2.1, 𝐼_𝐷=3.024 mA; an excellent match with the deviation being due to accumulated rounding errors.

In order to show the increased Q point stability of the combination bias, we’ll repeat the preceding problem using a JFET with a significantly lower 𝐼_𝐷𝑆𝑆.

The graph of Figure 1.4.15 illustrates nicely the increased stability of the Q point. Once again, we plot two representative device curves in green and blue. As was the case with self bias, a plot line can be drawn, the slope of which is equal to the reciprocal of 𝑅_𝑆. This plot line does not go though the origin, though. Instead, the 𝑥x axis intercept is the voltage |𝑉_𝑆𝑆|. Thus, the red plot line is shifted along the 𝑉_𝐺𝑆 axis.

As can be seen in the graph, the variation in 𝐼_𝐷 is reduced (although at the expense of variation in 𝑉_𝐺𝑆). For large values of 𝑉_𝑆𝑆 with correspondingly large values of 𝑅_𝑆, the bias plot line becomes nearly horizontal, indicating a very stable Q point. With two variables in play, this bias proves to be very flexible. It can also be realized by using a positive voltage divider at the gate and removing 𝑉_𝑆𝑆 (returning 𝑅_𝑆 to ground).

Constant Current Bias

The most stable bias for JFETs relies, oddly enough, on a current source made with a BJT. It is called constant current bias, yet another imaginative tag. Interestingly, although this will keep the Q point very stable, a fixed 𝐼_𝐷 does not guarantee the most stable value of voltage gain. In fact, it might be easier to achieve that goal using combination bias. The prototype constant current bias circuit is shown in Figure 1.4.16. An NPN BJT is used for an N-channel JFET and a PNP would be used with a P-channel JFET, typically driven from above (i.e., circuit flipped top to bottom).

Ignoring the JFET for a moment, the BJT is configured as in two-supply emitter bias. In this case the base is tied directly to ground, leaving the emitter at about −0.7 VDC. The remainder of the 𝑉_𝐸𝐸 supply drops across 𝑅_𝐸, establishing the emitter current. As the collector is connected directly to the JFET’s source terminal, this means that 𝐼_𝑆≈𝐼_𝐸. The source current winds up being just as stable as the emitter current, which we have already seen is very stable. The only requirement is that 𝐼_𝐸 should not be programmed to be larger than 𝐼_𝐷𝑆𝑆. This being true, 𝐼_𝐷 will set up a corresponding 𝑉_𝐺𝑆. This also establishes 𝑉_𝑆 because 𝑉_𝐺≈0. Therefore, the source terminal will be a small positive voltage and this is precisely what the BJT needs in order to guarantee that its collector-base junction is reverse-biased.

Computation of circuit currents and voltages is straightforward and does not involve the use of graphical aides. The first step is to examine the BJT’s emitter loop and determine 𝐼_𝐸. Once this is found, 𝐼_𝑆 and 𝐼_𝐷 are known, and all remaining component potentials may be found using Ohm’s law and KVL.

This technique does not involve the calculation of 𝑉_𝐺𝑆. In fact, because 𝐼_𝐷 is very stable, 𝑉_𝐺𝑆 will show the widest variation of all biasing circuits when the JFET is changed. If 𝑉_𝐺𝑆 is needed, it can be determined via a little algebraic manipulation on Equation 1.2.1.

Example 1.4.6

Determine 𝐼_𝐷, 𝑉_𝐷𝑆 and 𝑉_𝐺𝑆 in the circuit of Figure 1.4.17. 𝐼_𝐷𝑆𝑆 = 15 mA and 𝑉_{𝐺𝑆(𝑜𝑓𝑓)} = −3 V.

We begin by finding 𝐼_𝐸.

   

   

   

𝐼_𝐸 is the same as 𝐼_𝑆 and 𝐼_𝐷, therefore

   

   

   

To find 𝑉_𝑆 we note that 𝑉_𝑆=−𝑉_𝐺𝑆 and rearrange Equation 1.2.1.

   

   

   

   

Therefore 𝑉_𝑆=1.24V and

   

   

   

We turn next to a computer simulation of a similar circuit to validate our methodology.

Computer Simulation

A constant current bias circuit is entered into a simulator as shown in Figure 1.4.18.

A cursory estimate shows that 𝐼_𝐸 and 𝐼_𝐷 should be around 4.3 mA. Also, 𝑉_𝐷 should be approximately 20 V − 4.3 mA ⋅ 2.2 kΩ, or about 1.54 volts. The results of a DC operating point analysis are shown in Figure 1.4.19.

The drain voltage (node 3) is just over 1.6 volts, agreeing with our estimate. Also, note the minuscule gate voltage (node 1) of 12 𝜇V which verifies our continuing assumption in these circuits that 𝑉_𝐺≈0 V_DC. Finally, we see a modest potential of about 1.5 volts at the source terminal (node 12). This shows the proper reverse-biasing of both the gate-source and collector-base junctions.

Finally, we can examine the Q point variation using Figure 1.4.20. Here, the plot line is perfectly horizontal and all device variation is manifest in 𝑉_𝐺𝑆.